The present invention relates generally to a method for enhancing the testing of an electronic circuit, such as a circuit for use in a computer system. More particularly, the present technique improves the testing of an integrated circuit, such as an application specific integrated circuit (ASIC), by utilizing a more efficient method of managing an idle bus.
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In the past twenty years, great strides have been made in electronic circuitry. The electronic devices, such as transistors, that comprise integrated circuits have become much smaller, thus making the integrated circuits much denser. This increased density has lead to greatly enhanced functionality of integrated circuits. However, such enhanced functionality has come at the expense of complexity. Indeed, as compared to an integrated circuit made twenty years ago, today""s integrated circuits, as well as the electronic circuits in which such integrated circuits are used, are vastly more complex.
For example, today a conventional computer system typically includes one or more central processing units (CPUs) and one or more memory subsystems. A CPU typically includes at least one processor, such as a microprocessor, and supporting circuits, such as a host controller, bridges, and a memory controller. Computer systems also typically include peripheral devices for inputting and outputting data. Some common peripheral devices include, for example, monitors, keyboards, printers, modems, hard disk drives, floppy disk drives, and network controllers. The various components of computer system communicate and transfer data using various buses and other communication channels that interconnect the respective components. Such communication often takes place at frequencies of a few hundred megahertz to a few gigahertzxe2x80x94frequencies that were thought unreachable just a few years ago.
During the design phase of an electronic system, such as a computer system, each portion of the system is typically tested to ensure that the system will operate properly when produced. This type of testing is usually referred to as xe2x80x9cdebugging.xe2x80x9d Many integrated circuits, such as microprocessors and application specific integrated circuits (ASICs), are initially designed using software design tools. While in software, the person debugging the system may use any internal test point to understand the functions and issues that are presented. This is not the case once the circuit is actually reduced to hardware.
Once the integrated circuit is in hardware form, it includes a number of pins used for input, output, power, ground, etc. Generally, the input and output pins of an integrated circuit may be sampled externally when the circuit is in hardware. In testing the circuit, however, the input and output pins do not always help the person debugging the circuit, because many hardware issues within the circuit may not generate a signal on the input or output pins. Thus, to facilitate the testing of an integrated circuit, most integrated circuits include test pins in addition to the normal pins used for input, output, power, ground, etc. These test pins provide the debugger with access to some of the internal data points that may be useful in resolving a hardware problem.
A limitation associated with the test pins is that the number of internal test points that are desirable is much larger than the output pins that are available. Each pin on an integrated circuit increases its size, cost, and complexity. Thus, the number of test pins is often a compromise between adding to the size, cost, and complexity of the integrated circuit and providing debuggers with a useful number of signals. Generally speaking, it is desirable to have fewer test pins and more operational or functional pins because, while the test pins are needed in testing, once testing is completed the test pins are not used by the system to perform the task for which the integrated circuit was designed.
In an attempt to address this problem, a multiplexor circuit may be added to the integrated circuit to select a subset of the internal test points based on a software-configurable value. For example, if the integrated circuit includes 18 test pins and if the multiplexor circuit permits one of 32 groups of 18 internal test points to be sent to the test pins at any given time, the debuggers can choose up to 576 internal test points. Although such a technique allows the debugger to sample a relatively large number of internal signals using a relatively small number of test pins, the technique is not without its drawbacks. For example, a problem faced by a debugger involves the need to view simultaneously two or more signals in different sets of the 32 groups of 18 signals.
This problem can be somewhat alleviated by breaking up each of the groups of signals into sets using multiple selects. For instance, following the ongoing example, each group of 18 signals could be broken up into three sets of six signals each. While this provides debuggers with some additional flexibility, the absolute number of test signals available at any given time remains fixed. Also, designers can attempt to position signals carefully so that subsequent debuggers will have the best chance to see all of the necessary signals simultaneously. While this technique has also produced some desirable results, designers cannot accurately predict which signals will be needed in determining the root cause of a hardware problem.
As a result of these drawbacks, debuggers can often expend a significant amount of time troubleshooting a circuit to resolve failures. Therefore, it would be advantageous to have additional test data available to the user without using additional dedicated test pins and/or to reduce or eliminate the number of dedicated test pins while still providing access to internal test points for use in debugging the device.
The present invention may address one or more of the problems discussed above.